(i) Field of the Invention
The present invention relates to a high-voltage thin-film transistor and its manufacture method, especially to a high-voltage thin-film transistor constituting a thin-film circuit formed on an insulating substrate and an insulating layer.
(ii) Description of the Related Art
A high-voltage thin-film transistor is used to constitute a thin-film transistor which can be operated even if a high drain voltage is applied thereto. Conventional high-voltage thin-film transistor is disclosed in an article entitled "A Simpler 100-V Polysilicon TFT with Improved Turn-On Characteristics" by T. Y. Huang in IEEE Electron Devices Letters, pages 244 to 246, vol. 11, no. 6 (June 1990).
Specifically, as shown in FIG. 1, in the conventional high-voltage thin-film transistor, a source region 301, a drain region 302, and an active region 303 are formed on a substrate 300.
A main-gate electrode 305 is formed on a main-gate insulating layer 304 with thickness of 100 nm overlapping the active region 303. An offset region 306 with no impurities doped therein is formed between the active region 303 and the drain region 302. A sub-gate electrode 308 is formed on an interlayer insulating film 307 with thickness of 700 nm overlapping the offset region 306.
Operation of the aforementioned high-voltage thin-film transistor will be described with reference to FIG. 1. The conductivity of the offset region 306 can be controlled by a voltage applied to the sub-gate electrode 308. The drain electric field can be moderated by setting the sub-gate voltage to an appropriate value.
In the article, when a voltage slightly larger than the half of the drain voltage is applied, the drain electric field can be distributed at both ends of the offset region 306, so that dielectric breakdown properties can be optimized.
It is difficult to control a voltage of about 100V using such a high-voltage thin-film transistor to transmit a signal with amplitude of 5V to the main-gate electrode 304. In the article, when the drain voltage of about 100V is applied, the voltage applied to the sub-gate electrode is set to about 60V, but in order to prevent dielectric breakdown, the sub-gate insulating layer needs to be formed as thick as about 700 nm.
In this case, since the sub-gate insulating layer is thick, the density of charges induced to the offset region 306 is lowered and the resistance is raised, which causes a current pinching phenomenon.